In this issue of ACM SigArch Newsletter, we present ten papers from MEDEA-2005 Workshop held in conjunction with the IEEE/ACM Int.l Conf. on Parallel Architectures and Compilation Techniques (PACT-2004). Due to the ever-increasing gap between CPU and memory speed, the interest in evaluating and proposing architectures dealing with memory wall problems is still alive. In particular,  the problem of hiding/tolerating memory latencies is exacerbated by wire-delay and power consumption issues. Memory is far slower than processor, and its access is becoming even slower due to wire delay, which is not anymore negligible also in caches, especially large and high performance ones. On the other side, the need of maintaining low the overall chip energy dissipation pushes towards the reconsideration of the whole memory subsystem architecture. One of the most interesting approaches is based on decoupling resources, both on-chip and off-chip. In addition, modular high-level design is needed to reduce design costs. In this scenario, system design issues should be addressed taking into account the relationship between the system architecture and the run-time behavior of the particular application domain. In fact, it is the interaction between the static/dynamic features of the application and the system on which it executes that stresses the memory subsystem and pushes towards specific solutions.