As the number of transistors per computing system is ever-increasing, so are the fault rates. This issue may be critical also in the area of embedded systems, as they may work in mission-critical conditions and in contexts where they may be subject to several sources of faults. We propose to provide a further dimension of flexibility by federating the capabilities of several separated FPGA-based independent systems, so as to provide a more resilient system that can also improve the performance by simply joining more systems via an inexpensive and simple high-speed interconnect. Differently, from traditional checkpointing or lock-stepping, we foresee the possibility of relying on a disciplined data flow among the application threads. The underlying execution model is known as dataflow-threads (DF-threads) and the faultdetection extension of this model allows to achieve a resilient execution of an application while faults are affecting the system. In the proposed implementation, the execution time gracefully degrades as the number of faults increases,  without the need for global checkpointing and without interrupting the application execution. The technique has been evaluated on a fullsystem x86-64 simulator with encouraging results and an FPGA-based implementation is under development.